1. Field of the Invention
This invention relates to a manufacturing method for forming metal plugs, and, more particularly, to a method for forming metallic interconnection plugs within semiconductor components.
2. Description of Related Art
In the conventional process for manufacturing integrated circuits in general, with the exception of a few functionally simple circuits, such as mask ROMs or other moderately complex circuits in which components can be interconnected by a single polycide layer and a metallic layer, most moderate to complex integrated circuits require more complex schemes for circuit interconnection. As the size of the integrated circuits is decreased, sufficient surface area is not available to accomodate all the necessary interconnected wirings. As a result, semiconductor circuit designs having two or more metallic layers are becoming essential. In particular, for functionally complex circuits such as microprocessors, up to four or five metallic layers of interconnections are necessary to interconnect all circuit components.
In multi-layered metallic wiring systems, in order to avoid short-circuiting between different metallic wiring layers through direct contact (with the exception of designated contacting points), an insulating layer must be provided between the metallic layers. Such insulating layers are formed of dielectric material and are generally referred to in the art as the inter-layer dielectrics. To connect the different metallic layers in an integrated circuit, a metal plug is used.
FIGS. 1A through 1H show the conventional manufacturing method for forming metal plugs. First, on a silicon substrate 10, P-type or N-type ions are implanted to form a doped region 12 acting as a basic component for the integrated circuit, and in this example, an N-type implant is used. Then, a dielectric layer 14, for example, a silicon oxide or a silicon nitride layer, is formed above the silicon substrate 10. Using a photolithographic process (employing one mask), a contact window 15 is formed by etching the dielectric layer 14 until the silicon substrate surface for subsequent connection is reached. Thereafter, a layer of plug metal 16 (for example, tungsten) is deposited above the dielectric layer 14 and also filling the contact window 15, and then the plug metal layer 16 is etched back until the underlying surface of the dielectric layer 14 is exposed. Next, a conducting layer 18 is formed above the dielectric layer 14 and the exposed plug metal layer 16. Using another mask, a pattern is defined on the conducting layer 18, followed by the formation of another dielectric layer 20 on top of the patterned conducting layer 18. Again using another photolithographic process and yet another mask, the dielectric layer 20 is etched to form another contact window 21 which exposes the surface of the conducting layer 18 beneath for subsequent connection. Finally, another layer of plug metal 22 is deposited above the dielectric layer 20, filling the contact window 21, and then etched back until the dielectric layer 20 is exposed to form the metal plug 22.
Although much of the difficulties in metallic wiring interconnections presented by a conventional single metal layer or a single polycide layer design of integrated circuits are overcome by the foregoing method for forming a metal plug, there remain several deficiencies leaving room for improvement.
For example, in the conventional method for forming a metal plug, as described above, several separate photolithographic operations using different masks are required, which requires much production time and expense. Furthermore, repeated applications of tungsten deposition followed by etching back add complications to the overall manufacturing operation.